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ThinkMind // CENICS 2011, The Fourth International Conference on Advances in Circuits, Electronics and Micro-electronics // View article cenics_2011_1_20_60036


Design and Analysis of a Dual Loop CDR using Maneatis Delay Cell VCO

Authors:
Khalil Mahmoud
Dhurga Devi
P. Ramakrishna

Keywords: CDR, PLL, VCO, Jitter, Power Supply Noise

Abstract:
Clock and Data Recovery (CDR) circuits have been used extensively in the receivers of optical communication systems, and a variety of applications of inter and intra chip communications. The primary design/performance metrics of CDR circuits are clock jitter, lock range, acquisition time, power consumption, silicon area, and noise immunity. The main source of jitter is the power supply noise. The present paper investigates the effects of power supply noise on the jitter performance of the well known dual loop architecture of CDR system. In order to improve the jitter performance of the dual loop CDR system, the VCO alone is replaced by the self-biased Maneatis VCO which is well known for its immunity to power supply noise and process variations. The Maneatis VCO is widely used for microprocessors PLL systems but it is rarely used in CDR systems. The combination of the dual loop architecture and self-biased Maneatis VCO together provides the benefits of both schemes. Simulations were then carried out systematically to determine the capability of the proposed CDR circuit to tolerate power supply noise. The results presented in this paper show that while the conventional dual loop architecture cannot tolerate more than 20mV@10MHz noise on power supply terminal, the proposed CDR architecture can tolerate up to 200mV@10MHz noise on the power supply without degradations in jitter performance.

Pages: 6 to 12

Copyright: Copyright (c) IARIA, 2011

Publication date: August 21, 2011

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-150-2

Location: Nice/Saint Laurent du Var, France

Dates: from August 21, 2011 to August 27, 2011

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